1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a structure of a three-dimensional memory block having a stacked structure.
2. Description of the Related Art
With higher integration and finer design of a semiconductor integrated circuit, it is necessary to form an element in a smaller area in higher density. Particularly, in a semiconductor memory, one of important problems is to form an element in a smaller area in higher density to produce a memory at low cost per bit unit price.
However, conventionally in a multi-layer NAND flash memory which is one of the lowest-cost memories, further cost reduction becomes difficult due to difficulty in processing and a limit of a field effect transistor with reduction of a production rule.
On the other hand, a memory having a structure in which memory cells with no field effect transistor are three-dimensionally arrayed has been proposed as a memory in which memory elements are arrayed in higher density (for example, Japanese Patent Application Laid-Open No. 2003-78114). In some of memory cells used in the memory as disclosed in Japanese patent Publication Laid-Open No. 2003-78114, a memory element such as a phase change memory, a resistance change memory, and a conductance-bridge memory are used with a diode or a non-ohmic element which can bi-directionally restrict a current.
However, in the three-dimensional type memory, a structure of a peripheral circuit becomes complicated, and the chip-size reduction is hardly achieved in the peripheral circuit.